PCI Express* (D28:F0, F1)
11.2.14 MBL—Memory Base and Limit Register
Address Offset:
Default Value:
20h–23h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Accesses that are within the ranges specified in this register will be sent to the attached
device if the Memory Space Enable bit of PCICMD is set. Accesses from the attached
device that are outside the ranges specified will be forwarded to the internal Intel®
SCH message network if the Bus Master enable bit of PCICMD is set.
Default
Bit
and
Description
Access
Memory Limit (ML): These bits are compared with bits 31:20 of the
incoming address to determine the upper 1 MB aligned value of the
range.
000h
R/W
31:20
19:16
15:4
3:0
0h
RO
Reserved
Memory Base (MB): These bits are compared with bits 31:20 of the
incoming address to determine the lower 1 MB aligned value of the
range.
000h
R/W
0h
RO
Reserved
11.2.15 PMBL—Prefetchable Memory Base and Limit Register
Address Offset:
Default Value:
24h–27h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Accesses that are within the ranges specified in this register will be sent to the device if
the Memory Space Enable bit of PCICMD is set. The comparison performed is:
PMBU32.PMB ≥ AD[63:32]:AD[31:20] ≤ PMLU32.PML.
Accesses from the device that are outside the ranges specified will be forwarded to the
backbone if the Bus Master enable bit of PCICMD is set.
Default
Bit
and
Description
Access
Prefetchable Memory Limit (PML): These bits are compared with
bits 31:20 of the incoming address to determine the upper 1 MB aligned
value of the range.
000h
R/W
31:20
19:16
15:4
3:0
0h
RO
64-bit Indicator (I64L): Indicates support for 64-bit addressing
Prefetchable Memory Base (PMB): These bits are compared with
bits 31:20 of the incoming address to determine the lower 1 MB aligned
value of the range.
000h
R/W
0h
RO
64-bit Indicator (I64B): Indicates support for 64-bit addressing
Datasheet
183
INTEL [ INTEL ]
