PCI Express* (D28:F0, F1)
11.2.16 CAP_PTR—Capabilities Pointer Register
Address Offset:
Default Value:
34h
40h
Attribute:
Size:
R0
8 bits
Default
and
Bit
Description
Access
40h
RO
Pointer (PTR): Indicates that the pointer for the first entry in the
capabilities list is at offset 40h in configuration space.
7:0
11.2.17 INT_LN—Interrupt Line Register
Address Offset:
Default Value:
3Ch
00h
Attribute:
Size:
R/W
8 bits
Default
Bit
and
Description
Access
Interrupt Line (INT_LN): This data is not used by the Intel® SCH. It is
used as a scratchpad register to communicate to software the interrupt
line that the interrupt pin is connected to.
00h
R/W
7:0
11.2.18 INT_PN—Interrupt Pin Register
Address Offset:
Default Value:
3Dh
Attribute:
Size:
RO
8 bits
See bit description
Default
Bit
and
Description
Access
Interrupt Pin (IPIN): This value tells the software which interrupt pin
each PCI Express port uses. The upper 4 bits are hardwired to 0000b; bits
3:0 are determined by the Interrupt Pin default values programmed in the
memory-mapped configuration space as follows:
0xh
RO
7:0
Port 1
Port 2
D28IP.P1IP (Offset 310Ch, bits 3:0)
D28IP.P2IP (Offset 310Ch, bits 7:4)
NOTE: This does not determine the mapping to the PIRQ pins.
184
Datasheet
INTEL [ INTEL ]
