PCI Express* (D28:F0, F1)
11.2.24 DCTL—Device Control Register
Address Offset:
Default Value:
48h–49h
0000h
Attribute:
Size:
R/W, RO
16 bits
Default
and
Bit
Description
Access
0
RO
15
14:12
11
Reserved
000b
RO
Max Read Request Size (MRRS): Hardwired to 0.
0
RO
Enable No Snoop (ENS): Not supported. The root port will never issue
non-snoop requests.
Aux Power PM Enable (APME): The OS will set this bit to 1 if the device
connected has detected aux power. It has no effect on the root port
otherwise.
0
R/W
10
0
RO
9
8
Phantom Functions Enable (PFE): Not supported.
Extended Tag Field Enable (ETFE): Not supported.
0
RO
000b
R/W
Max Payload Size (MPS): The root port only supports 128-B payloads,
regardless of the programming of this field.
7:5
4
0
RO
Enable Relaxed Ordering (ERO): Not supported.
Unsupported Request Reporting Enable (URE):
0 = The root port will ignore unsupported request errors.
1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the
Root Control register when detecting an unmasked Unsupported
Request (UR). An ERR_COR is signaled when a unmasked Advisory
Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent
to the Root Control Register when an uncorrectable non-Advisory UR
is received with the severity set by the Uncorrectable Error Severity
register.
0
R/W
3
Fatal Error Reporting Enable (FEE):
0 = The root port will ignore fatal errors.
0
R/W
2
1
0
1 = Enables signaling of ERR_FATAL to the Root Control register due to
internally detected errors or error messages received across the link.
Other bits also control the full scope of related error reporting.
Non-Fatal Error Reporting Enable (NFE):
0 = The root port will ignore non-fatal errors.
0
R/W
1 = Enables signaling of ERR_NONFATAL to the Root Control register due
to internally detected errors or error messages received across the
link. Other bits also control the full scope of related error reporting.
Correctable Error Reporting Enable (CEE):
0 = The root port will ignore correctable errors.
0
R/W
1 = Enables signaling of ERR_CORR to the Root Control register due to
internally detected errors or error messages received across the link.
Other bits also control the full scope of related error reporting.
188
Datasheet
INTEL [ INTEL ]
