PCI Express* (D28:F0, F1)
11.2.23 DCAP—Device Capabilities Register
Address Offset:
Default Value:
44h–47h
00008FC0h
Attribute:
Size:
RO
32 bits
Default
Bit
and
Description
Access
0h
RO
31:28
27:26
25:18
17:16
Reserved
00b
RO
Captured Slot Power Limit Scale (CSPS): Not supported.
Captured Slot Power Limit Value (CSPV): Not supported.
Reserved
00h
RO
00b
RO
Role Based Error Reporting (RBER): Indicates that this device
implements the functionality defined in the Error Reporting ECN as
required by the PCI Express 1.1 specification.
1
RO
15
0
RO
Power Indicator Present (PIP): This bit indicates no power indicator is
present on the root port.
14
13
12
0
RO
Attention Indicator Present (AIP): This bit indicates no attention
indicator is present on the root port.
0
RO
Attention Button Present (ABP): This bit indicates no attention button
is present on the root port.
Endpoint L1 Acceptable Latency (E1AL): This field indicates more than
4 µs. This field essentially has no meaning for root ports since root ports
are not endpoints.
111b
RO
11:9
8:6
Endpoint L0 Acceptable Latency (E0AL): This field indicates more than
64 µs. This field essentially has no meaning for root ports since root ports
are not endpoints.
111b
RO
0
RO
Extended Tag Field Supported (ETFS): This bit indicates that 8-bit tag
fields are supported.
5
00b
RO
Phantom Functions Supported (PFS): No phantom functions
supported.
4:3
2:0
000b
RO
Max Payload Size Supported (MPS): This field indicates the maximum
payload size supported is 128 Bytes.
Datasheet
187
INTEL [ INTEL ]
