PCI Express* (D28:F0, F1)
11.2.12 IOBL—I/O Base and Limit Register
Address Offset:
Default Value:
1Ch–1Dh
0000h
Attribute:
Size:
R/W, RO
16 bits
Default
and
Bit
Description
Access
0h
R/W
I/O Limit Address (IOLA): I/O Base bits corresponding to address lines
15:12 for 4 KB alignment. Bits 11:0 are assumed to be padded to FFFh.
15:12
11:8
7:4
0h
RO
I/O Limit Address Capability (IOLC): Indicates that the bridge does
not support 32-bit I/O addressing.
0h
R/W
I/O Base Address (IOBA): I/O Base bits corresponding to address lines
15:12 for 4 KB alignment. Bits 11:0 are assumed to be padded to 000h.
0h
RO
I/O Base Address Capability (IOBC): Indicates that the bridge does
not support 32-bit I/O addressing.
3:0
11.2.13 SSTS—Secondary Status Register
Address Offset:
Default Value:
1Eh–1Fh
0000h
Attribute:
Size:
R/WC, RO
16 bits
Default
and
Bit
Description
Access
Detected Parity Error (DPE)
0
15
0 = No error.
1 = The port received a poisoned TLP.
R/WC
Received System Error (RSE)
0
0 = No error.
14
13
12
R/WC
1 = The port received an ERR_FATAL or ERR_NONFATAL message from
the device.
Received Master Abort (RMA)
0
0 = Unsupported Request not received.
1 = The port received a completion with “Unsupported Request” status
from the device.
R/WC
Received Target Abort (RTA)
0
0 = Completion Abort not received.
1 = The port received a completion with “Completion Abort” status from
the device.
R/WC
0
RO
Signaled Target Abort (STA): Reserved. The Intel® SCH cannot
generate a target abort.
11
00
RO
Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI
Express Base Specification.
10:9
Data Parity Error Detected (DPD)
0 = Conditions below did not occur.
1 = Set when the BCTRL.PERE (D28:F0/F13E: bit 0) is set, and either of
the following two conditions occurs:
0
8
R/WC
• Port receives completion marked poisoned.
• Port poisons a write request to the secondary side.
00h
RO
7:0
Reserved
182
Datasheet
INTEL [ INTEL ]
