PCI Express* (D28:F0, F1)
11.2.6
CC—Class Codes Register
Address Offset:
Default Value:
09h–0Bh
060400h
Attribute:
Size:
RO
24 bits
Default
and
Bit
Description
Access
06h
RO
23:16
15:8
7:0
Base Class Code (BCC): 06h indicates the device is a bridge device.
Sub Class Code (SCC): 04h indicates this is a PCI-to-PCI bridge.
04h
RO
00h
RO
Programming Interface (PI): No specific register level programming
interface defined.
11.2.7
11.2.8
CLS—Cache Line Size Register
Address Offset:
Default Value:
0Ch
00h
Attribute:
Size:
R/W
8 bits
Default
and
Bit
Description
Access
00h
R/W
Cache Line Size (CLS): This is read/write but contains no functionality,
per the PCI Express Base Specification.
7:0
PLT—Primary Latency Timer Register
Address Offset:
Default Value:
0Dh
00h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
0h
RO
7:3
2:0
Latency Count (CT): Reserved per the PCI Express Base Specification.
000b
RO
Reserved
180
Datasheet
INTEL [ INTEL ]
