PCI Express* (D28:F0, F1)
11.2.4
PCISTS—PCI Status Register
Address Offset:
Default Value:
06h–07h
0010h
Attribute:
Size:
R/WC, RO
16 bits
Note:
There is a secondary status register (SSTS) located at offset 1Eh.
Default
Bit
and
Description
Access
0
RO
15
Reserved
Signaled System Error (SSE)
0
0 = No system error signaled.
1 = Set when the root port signals a system error to the internal SERR#
logic.
14
R/WC
000h
RO
13:5
4
Reserved
1
RO
Capabilities List (CLIST): Hardwired to 1 indicating the presence of a
capabilities list (at offset 34h)
Interrupt Status (IS): Indicates status of hot-plug and power
management interrupts on the root port that result in INTx# message
generation.
0
RO
3
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
This bit is set regardless of the state of PCICMD.Interrupt Disable bit
(D28:F0/F1:04h:bit 10).
000b
RO
2:0
Reserved
11.2.5
RID—Revision Identification Register
Offset Address:
Default Value:
08h
Attribute:
Size:
RO
8 bits
See description
Default
Bit
and
Description
Access
See
Description
RO
Revision ID (RID): Refer to the Intel® System Controller Hub (Intel®
SCH) Specification Update for the value of the Revision ID Register.
7:0
Datasheet
179
INTEL [ INTEL ]
