PCI Express* (D28:F0, F1)
11.2.3
PCICMD—PCI Command Register
Address Offset:
Default Value:
04h–05h
0000h
Attribute:
Size:
R/W, RO
16 bits
Default
Bit
and
Description
Access
0h
RO
15:11
Reserved
Interrupt Disable (ID): This bit disables pin-based INTx# interrupts on
enabled hot-plug and power management events.
0 = Internal INTx# messages are generated if there is an interrupt for
hot-plug or power management.
1 = Internal INTx# messages will not be generated.
0
R/W
10
This bit does not effect interrupt forwarding from devices connected to the
root port. Assert_INTx and Deassert_INTx messages will still be
forwarded to the internal interrupt controllers if this bit is set.
0
RO
9
8
Reserved
0
R/W
SERR# Enable (SEE): Hardwired to 0 to indicate this port cannot
generate SERR# messages.
0h
RO
7:3
Reserved
Bus Master Enable (BME)
0
R/W
0 = Disable. All cycles from the device are master aborted
1 = Enable. Allows the root port to forward cycles onto the backbone from
a PCI Express device.
2
1
Memory Space Enable (MSE)
0 = Disable. Memory cycles within the range specified by the memory
base and limit registers are master aborted on the backbone.
1 = Enable. Allows memory cycles within the range specified by the
memory base and limit registers can be forwarded to the PCI Express
device.
0
R/W
I/O Space Enable (IOSE): This bit controls access to the I/O space
registers.
0
R/W
0 = Disable. I/O cycles within the range specified by the I/O base and
limit registers are master aborted on the backbone.
0
1 = Enable. Allows I/O cycles within the range specified by the I/O base
and limit registers can be forwarded to the PCI Express device.
178
Datasheet
INTEL [ INTEL ]
