PCI Express* (D28:F0, F1)
Table 29.
PCI Express* Register Address Map (Sheet 2 of 2)
Offset
Mnemonic
DCTL
Register Name
Device Control
Default
0000h
Type
48h–49h
4ah–4bh
4Ch–4Fh
50h–51h
R/W, RO
DSTS
LCAP
LCTL
Device Status
Link Capabilities
Link Control
0010h
R/WC, RO
RO, R/WO
R/W, WO, RO
00054C11h
0000h
See
description
52h–53h
LSTS
Link Status
RO
54h–57h
58h–59h
SLCAP
SLCTL
Slot Capabilities
Slot Control
00000060h
0000h
R/WO, RO
R/W, RO
See
description
5Ah–5Bh
SLSTS
Slot Status
R/WC, RO
5Ch–5Dh
5Eh
RCTL
Root Control
0000h
xxxxh
00000000h
0dh
R/W, RO
RO
RCAP
Root Capabilities
60h–63h
90h
RSTS
Root Status
R/WC, RO
RO
SV_CAPID
NXT_PTR3
SVID
Subsystem Vendor Capability ID
Next Item Pointer #3
Subsystem Vendor Identification
91h
A0h
RO
94h–97h
A0h
00h
R/WO
RO
PM_CAPID
NXT_PTR4
PM_CAP
Power Management Capability ID 01h
A1h
Next Item Pointer #4
00h
RO
A2h–A3h
Power Management Capabilities
C802h
RO
Power Management Control/
Status
A4–A7h
PM_CNTL_STS
00000000h
R/W, RO
D8–Dbh
DC–DFh
FCh–FFh
MPC
Miscellaneous Port Configuration
SMI/SCI Status
00110000h
00000000h
00000000h
R/W, RO
R/WC, RO
R/W, RO
SMSCS
FD
Function Disable
NOTE: Address locations that are not shown should be treated as Reserved.
176
Datasheet
INTEL [ INTEL ]
