PCI Express* (D28:F0, F1)
11.1.4
Additional Clarifications
11.1.4.1
Non-Snoop Cycles Are Not Supported
The Intel® SCH does not support No Snoop cycles on PCIe. DCTL.ENS can never be
set. Platform BIOS must disable generation of these cycles in all installed PCIe devices.
Generation of a No Snoop request by a PCIe device may result in a protocol violation
and lead to errors.
For example, a no-snoop read by a device may be returned by a snooped completion,
and this attribute difference, a violation of the specification, will cause the device to
ignore the completion.
11.2
PCI Express* Configuration Registers
Table 29.
PCI Express* Register Address Map (Sheet 1 of 2)
Offset
Mnemonic
VID
Register Name
Vendor Identification
Default
8086h
Type
00h–01h
RO
RO
See
Description
02h–03h
DID
Device Identification
04h–05h
06h–07h
PCICMD
PCISTS
PCI Command
PCI Status
0000h
0010h
R/W, RO
R/WC, RO
See
Description
08h
RID
Revision Identification
RO
09h–0Bh
0Ch
CC
Class Codes
060400h
00h
RO
CLS
Cache Line Size
R/W
0Dh
PLT
Primary Latency Timer
Header Type
00h
RO
0Eh
HEADTYP
BNUM
SLT
81h
RO
18h–1Ah
1Bh
Bus Number
000000h
0h
R/W
Secondary Latency Timer
I/O Base and Limit
Secondary Status
Memory Base and Limit
RO
1Ch–1Dh
1Eh–1Fh
20h–23h
IOBL
SSTS
MBL
0000h
0000h
00000000h
R/W, RO
R/WC, RO
R/W, RO
Prefetchable Memory Base and
Limit
24h–27h
PMBL
00010001h
R/W, RO
34h
3ch
CAP_PTR
INT_LN
Capabilities Pointer
Interrupt Line
40h
00h
RO
R/W
See
description
3dh
INT_PN
Interrupt Pin
RO
3Eh–3Fh
40h
BCTRL
Bridge Control
0000h
10
R/W, RO
RO
PCIE_CAPID
NXT_PTR1
PCIECAP
DCAP
PCI Express Capability ID
Next Item Pointer #1
PCI Express Capabilities
Device Capabilities
41h
90h
RO
42h–43h
44h–47h
0041
R/WO, RO
RO
00000FE0h
Datasheet
175
INTEL [ INTEL ]
