PCI Express* (D28:F0, F1)
11.1.2.2
11.1.2.3
Resuming From Suspended State
The root port can detect a wake event through the WAKE# signal and wake the system.
When the root port detects a WAKE# assertion, an internal signal is sent to the power
management controller of the Intel® SCH to cause the system to wake up. This
internal message is not logged in any register, nor is an interrupt/GPE generated.
Device Initiated PM_PME Message
When the system has returned to a working state from a previous low power state, a
device requesting service will send a PM_PME message continuously, until acknowledge
by the root port. The root port will take different actions depending upon whether this
is the first PM_PME has been received, or whether a previous message has been
received but not yet serviced by the operating system.
If this is the first message received (RSTS.PS - D28:F0/F1:Offset 60h:bit 16 is
cleared), the root port will set RSTS.PS, and log the PME Requester ID into RSTS.RID
(D28:F0/F1:Offset 60h:bits 15:0). If an interrupt is enabled by RCTL.PIE (D28:F0/
F1:Offset 5Ch:bit 3), an interrupt will be generated. This interrupt can be either a pin
or an MSI if MSI is enabled by MSI_CTL.MSIE (D28:F0/F1:Offset 82h:bit 0). See
Section 11.1.2.4 for SMI/SCI generation.
If this is a subsequent message received (RSTS.PS is already set), the root port will set
RSTS.PP (D28:F0/F1:Offset 60h:bit 17) and log the PME Requester ID from the
message in a hidden register. No other action will be taken.
When the first PME event is cleared by software clearing RSTS.PS, the root port will set
RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into
RSTS.RID.
If RCTL.PIE is set, generate an interrupt. If RCTL.PIE is not set, send over to the power
management controller so that a GPE can be set. If messages have been logged
(RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be
generated. This last condition handles the case where the message was received prior
to the operating system re-enabling interrupts after resuming from a low power state.
11.1.2.4
SMI/SCI Generation
Interrupts for power management events are not supported on legacy operating
systems. To support power management on non-PCI Express aware operating systems,
PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.
When set, a power management event will cause SMSCS.PMCS (D28:F0/F1:Offset
DCh:bit 31) to be set.
Additionally, BIOS workarounds for power management can be supported by setting
MPC.PMME (D28:F0/F1:Offset D8h:bit 0). When this bit is set, power management
events will set SMSCS.PMMS (D28:F0/F1:Offset DCh:bit 0), and SMI # will be
generated. This bit will be set regardless of whether interrupts or SCI is enabled. The
SMI# may occur concurrently with an interrupt or SCI.
11.1.3
Hot-Plug
The Intel® SCH does not support PCI Express Hot-Plug.
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Datasheet
INTEL [ INTEL ]
