PCI Express* (D28:F0, F1)
11 PCI Express* (D28:F0, F1)
11.1
Functional Description
There are two PCI Express root ports available in the Intel® SCH. They reside in device
28 and take function 0 and 1. Port 1 is function 0 and Port 2 is function 1.
11.1.1
Interrupt Generation
If enabled to do so, the Intel® SCH PCI Express root port generates interrupts as a
result of power management events. These interrupts can be communicated either by
legacy interrupt pins (internal to the Intel® SCH), or as Message Signal Interrupt
messages to the FSB. For the legacy pin behavior, the D28IP (Base address + 310Ch)
and D28IR (Base address + 3146h) registers can be configured to drive a particular
internal interrupt signal.
The following table summarizes interrupt behavior for MSI and wire modes. In the
table, “bits” refers to the PME interrupt bits.
Table 28.
MSI vs. PCI IRQ Actions
Wire-Mode
Interrupt Register
MSI Action
No action
Action
All bits are 0
Wire inactive
Wire active
Wire active
One or more bits set to 1
Send message
Send message
One or more bits set to 1, new bit gets set to 1
One or more bits set to 1, software clears some (but not
all) bits
Wire active
Wire inactive
Wire active
Send message
No action
One or more bits set to 1, software clears all bits
Software clears one or more bits, and one or more bits are
set on the same clock
Send message
11.1.2
Power Management
11.1.2.1
Sleep State Support
Software initiates the transition to S3/S4/S5 by performing an I/O write to the Power
Management Control register. After the I/O write completion has been returned to the
processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet)
message on it's downstream link. The device attached to the link will eventually
respond with a PME_TO_Ack TLP message followed by sending a PM_Enter_L23 DLLP
(Data Link Layer Packet) request to enter the L2/L3 Ready state. When all of the Intel®
SCH root ports links are in the L2/L3 Ready state, the Intel® SCH power management
control logic will proceed with the entry into S3/S4/S5.
Prior to entering S3, software is required to put each device into D3HOT. When a device
is put into D3HOT it will initiate entry into a L1 link state by sending a PM_Enter_L1
DLLP. Thus under normal operating conditions when the root ports sends the
PME_Turn_Off message the link will be in state L1. However, when the root port is
instructed to send the PME_Turn_Off message, it will send it whether or not the link
was in L1. Endpoints attached to ICH can make no assumptions about the state of the
link prior to receiving a PME_Turn_Off message.
Datasheet
173
INTEL [ INTEL ]
