Intel® HD Audio (D27:F0)
10.4.6
EM2—Extended Mode 2 Register
Memory Address:
Default Value:
1030h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
0
RO
31:9
8
Reserved
CORB Reset Pointer Change Disable (CORPRPDIS): When cleared,
CORBRP.RPR works as described. When this bit is set, the CORB FIFO is not
reset and CORBRP.RPR is WO and always read as 0.
0
R/W
0h
RO
7:0
Reserved
10.4.7
WLCLKA—Wall Clock Counter Alias Register
Memory Address:
Default Value:
2030h
00000000h
Attribute:
Size:
RO
32 bits
Default
Bit
and
Description
Access
Wall Clock Counter Alias (CounterA): Alias of WALCK. 32-bit counter
that is incremented on each link H_CLKIN period and rolls over from
FFFF_FFFFh to 0000_0000h. This counter will roll over to zero with a
period of approximately 179 seconds.
0
RO
31:0
This counter is enabled while the H_CLKIN bit is set to 1. Software uses
this counter to synchronize between multiple controllers. Will be reset on
controller reset.
10.4.8
SLPIB—Stream Link Position in Buffer Register
Memory Address:
Input Stream 0: 2084h
Input Stream 1: 20A4h
Output Stream 0: 2104h
Output Stream 2: 2124h
00000000h
Attribute: RO
Default Value:
Size:
32 bits
Default
Bit
and
Description
Access
Position (POS): Alias of the corresponding LPIB. Indicates the number of
bytes that have been received off the link. It counts from 0 to the value in
the Cyclic Buffer Length register and wraps.
0
RO
31:0
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Datasheet
INTEL [ INTEL ]
