Intel® HD Audio (D27:F0)
10.4.4
FIFOTRK – FIFO Tracking Register
Memory Address:
Default Value:
100Ch
000FF800h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
000h
RO
31:20
Reserved
Minimum Status (MSTS): Tracks the minimum FIFO free count for
inbound engines, and the minimum avail count for outbound engines when
EN is set and R is deasserted. The FIFO of the DMA selected by SEL is
tracked.
1FFh
RO
19:11
10:5
Error Count (EC): Increments each time a FIFO error occurs in the FIFO
which the DMA select is pointing to when the enable bit is set and R is
deasserted. When EC reaches a max count of 1FFh (63), the count
saturates and holds the max count until it is reset.
000h
RO
Select (SEL): MSTS and EC track the FIFO for the DMA select by this
register, as follows:
000 = Output DMA 0
001 = Output DMA 1
010 = Reserved
000b
R/W
4:2
011 = Reserved
100 = Input DMA 0
101 = Input DMA 1
110 = Reserved
111 = Reserved
0
R/W
Enable (EN): When set, MSTS and EC track the minimum FIFO status or
error count. When cleared, MSTS and EC hold its previous value.
1
0
0
R/W
Reset (R): When set, MSTS and EC are reset to their default value.
10.4.5
SDPIB—Stream DMA Position in Buffer Register
Memory Address:
Input Stream 0: 1010h
Input Stream 1: 1014h
Output Stream 0: 1020h
Output Stream 2: 1024h
00000000h
Attribute: RO
Default Value:
Size:
32 bits
Default
Bit
and
Description
Access
Position (POS): Indicates the number of bytes processed by the DMA
engine from the beginning of the BDL. For output streams, it is
incremented when data is loaded into the FIFO.
0
RO
31:0
Datasheet
171
INTEL [ INTEL ]
