Intel® HD Audio (D27:F0)
10.3.23 RINTCNT—Response Interrupt Count Register
Memory Address:
Default Value:
LBAR + 5Ah
0000h
Attribute:
Size:
R/W, RO
16 bits
Default
Bit
and
Description
Access
00h
RO
15:8
Reserved
N Response Interrupt Count
0000 0001b = 1 response sent to RIRB
...........
1111 1111b = 255 responses sent to RIRB
0000 0000b = 256 responses sent to RIRB
00h
R/W
The DMA engine should be stopped when changing this field or else an
interrupt may be lost.
7:0
Note that each response occupies 2 DWords in the RIRB.
This is compared to the total number of responses that have been
returned, as opposed to the number of frames in which there were
responses. If more than one codecs responds in one frame, then the count
is increased by the number of responses received in the frame.
10.3.24 RIRBCTL—RIRB Control Register
Memory Address:
Default Value:
LBAR + 5Ch
00h
Attribute:
Size:
R/W, RO
8 bits
Default
Bit
and
Description
Access
0h
RO
7:3
2
Reserved
Response Overrun Interrupt Control: If this bit is set, the hardware
will generate an interrupt when the Response Overrun Interrupt Status bit
(LBAR + 5Dh: bit 2) is set.
0
R/W
Enable RIRB DMA Engine:
0 = DMA stop
1 = DMA run
0
1
0
After software writes a 0 to this bit, the hardware may not stop
immediately. The hardware will physically update the bit to 0 when the
DMA engine is truly stopped. Software must read a 0 from this bit to
verify that the DMA engine is truly stopped.
R/W
Response Interrupt Control:
0 = Disable Interrupt
0
R/W
1 = Generate an interrupt after N number of responses are sent to the
RIRB buffer OR when an empty Response slot is encountered on all
SDI[x] inputs (whichever occurs first). The N counter is reset when
the interrupt is generated.
Datasheet
157
INTEL [ INTEL ]
