Intel® HD Audio (D27:F0)
10.3.21 RIRBBASE—RIRB Base Address Register
Memory Address:
Default Value:
LBAR + 50h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
CORB Lower Base Address: This field is the lower address of the
Response Input Ring Buffer, allowing the RIRB base address to be assigned
on any 128-B boundary. This register field must not be written when the
DMA engine is running or the DMA transfer may be corrupted.
0s
R/W
31:7
6:0
00h
RO
Reserved
10.3.22 RIRBWP—RIRB Write Pointer Register
Memory Address:
Default Value:
LBAR + 58h
0000h
Attribute:
Size:
WO, RO
16 bits
Default
Bit
and
Description
Access
RIRB Write Pointer Reset: Software writes a 1 to this bit to reset the
RIRB Write Pointer to 0. The RIRB DMA engine must be stopped prior to
resetting the Write Pointer or else DMA transfer may be corrupted.
0
WO
15
This bit is always read as 0.
00h
RO
14:8
Reserved
RIRB Write Pointer (RIRBWP): This field is the indicates the last valid
RIRB entry written by the DMA controller. Software reads this field to
determine how many responses it can read from the RIRB. The value read
indicates the RIRB Write Pointer offset in 2-DWord RIRB entry units (since
each RIRB entry is 2 dwords long). Supports up to 256 RIRB entries
(256 x 8 bytes = 2KB). This register field may be written when the DMA
engine is running.
00h
RO
7:0
156
Datasheet
INTEL [ INTEL ]
