Intel® HD Audio (D27:F0)
10.3.25 RIRBSTS—RIRB Status Register
Memory Address:
Default Value:
LBAR + 5Dh
00h
Attribute:
Size:
R/WC, RO
8 bits
Default
Bit
and
Description
Access
0h
RO
7:3
Reserved
Response Overrun Interrupt Status: Software sets this bit to 1 when
the RIRB DMA engine is not able to write the incoming responses to
memory before additional incoming responses overrun the internal FIFO.
When the overrun occurs, the hardware will drop the responses which
overrun the buffer. An interrupt may be generated if the Response Overrun
Interrupt Control bit is set. Note that this status bit is set even if an
interrupt is not enabled for this event.
0
2
R/WC
Software clears this bit by writing a 1 to it.
0
RO
1
0
Reserved
Response Interrupt: Hardware sets this bit to 1 when an interrupt has
been generated after N number of Responses are sent to the RIRB buffer
OR when an empty Response slot is encountered on all SDI[x] inputs
(whichever occurs first). Note that this status bit is set even if an interrupt
is not enabled for this event.
0
R/WC
Software clears this bit by writing a 1 to it.
10.3.26 RIRBSIZE—RIRB Size Register
Memory Address:
Default Value:
LBAR + 5Eh
40h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
0100b
RO
RIRB Size Capability: Hardwired to 0100b indicating that the Intel® SCH
only supports a RIRB size of 256 RIRB entries (2048 B).
7:4
3:2
1:0
00b
RO
Reserved
00b
RO
RIRB Size: Hardwired to 10b which sets the CORB size to 256 entries
(2048 B).
158
Datasheet
INTEL [ INTEL ]
