Intel® HD Audio (D27:F0)
10.3.13 WALCLK—Wall Clock Counter Register
Memory Address:
Default Value:
LBAR + 30h
00000000h
Attribute:
Size:
RO
32 bits
Default
Bit
and
Description
Access
Wall Clock Counter: This field is a 32-bit counter that is incremented on
each link H_CLKIN period and rolls over from FFFF FFFFh to 0000 0000h.
This counter will roll over to 0 with a period of approximately 179 seconds.
0s
RO
31:0
This counter is enabled while the H_CLKIN bit is set to 1. Software uses
this counter to synchronize between multiple controllers. Will be reset on
controller reset.
10.3.14 SSYNC—Stream Synchronization Register
Memory Address:
Default Value:
LBAR + 38h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bits
and
Description
Access
0
RO
31:4
Reserved
0
R/W
Output Stream 2 Sync (OS2): When set, this bit blocks data from being
sent for output stream 2.
3
2
1
0
0
R/W
Output Stream 1 Sync (OS1): When set, this bit blocks data from being
sent for output stream 1.
0
R/W
Input Stream 2 Sync (IS2): When set, this bit blocks data from being
received from input stream 2.
0
R/W
Input Stream 1 Sync (IS1): When set, this bit blocks data from being
received from input stream 1.
10.3.15 CORBBASE—CORB Base Address Register
Memory Address:
Default Value:
LBAR + 40h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
CORB Base Address: This field is the lower address of the Command
Output Ring Buffer, allowing the CORB base address to be assigned on any
128-B boundary. This register field must not be written when the DMA
engine is running or the DMA transfer may be corrupted.
0
R/W
31:7
6:0
0
RO
Reserved
Datasheet
153
INTEL [ INTEL ]
