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319537-003US 参数 Datasheet PDF下载

319537-003US图片预览
型号: 319537-003US
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔系统控制器中心 [Intel System Controller Hub]
分类和应用: 控制器
文件页数/大小: 450 页 / 2593 K
品牌: INTEL [ INTEL ]
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Intel® HD Audio (D27:F0)  
10.3.18 CORBCTL—CORB Control Register  
Memory Address:  
Default Value:  
LBAR + 4Ch  
00h  
Attribute:  
Size:  
R/W, RO  
8 bits  
Default  
Bit  
and  
Description  
Access  
00h  
RO  
7:2  
Reserved  
Enable CORB DMA Engine:  
0 = DMA stop  
1 = DMA run  
0
1
0
After software writes a 0 to this bit, the hardware may not stop  
immediately. The hardware will physically update the bit to 0 when the  
DMA engine is truly stopped. Software must read a 0 from this bit to verify  
that the DMA engine is truly stopped.  
R/W  
0
R/W  
CORB Memory Error Interrupt Enable: If this bit is set, the controller  
will generate an interrupt if the CMEI status bit (LBAR + 4Dh: bit 0) is set.  
10.3.19 CORBST—CORB Status Register  
Memory Address:  
Default Value:  
LBAR + 4dh  
00h  
Attribute:  
Size:  
RO  
8 bits  
Default  
Bit  
and  
Description  
Access  
7:0  
00h  
Reserved  
10.3.20 CORBSIZE—CORB Size Register  
Memory Address:  
Default Value:  
LBAR + 4Eh  
42h  
Attribute:  
Size:  
RO  
8 bits  
Default  
Bit  
and  
Description  
Access  
0100b  
RO  
CORB Size Capability: Hardwired to 0100b indicating that the Intel®  
SCH only supports a CORB size of 256 CORB entries (1024B).  
7:4  
3:2  
1:0  
00b  
RO  
Reserved  
10b  
RO  
CORB Size: Hardwired to 10b which sets the CORB size to 256 entries  
(1024 B).  
Datasheet  
155