Intel® HD Audio (D27:F0)
10.3.31 SDCTL—Stream Descriptor Control Register
Memory Address:
Input Stream[0]: LBAR + 80h
Input Stream[1]: LBAR + A0h
Output Stream[0]: LBAR + C0h
Output Stream[1]: LBAR + E0h
040000h
Attribute: R/W, RO
Default Value:
Size:
24 bits
Default
Bit
and
Description
Access
Stream Number: This value reflect the Tag associated with the data being
transferred on the link.
When data controlled by this descriptor is sent out over the link, it will have
its stream number encoded on the HDA_SYNC signal.
When an input stream is detected on any of the SDI signals that match this
value, the data samples are loaded into FIFO associated with this
descriptor.
0h
R/W
23:20
Note that while a single SDI input may contain data from more than one
stream number, two different SDI inputs may not be configured with the
same stream number.
0000 = Reserved
0001 = Stream 1
........
1110 = Stream 14
1111 = Stream 15
0
RO
Bidirectional Direction Control: This bit is only meaningful for
bidirectional streams; therefore, this bit is hardwired to 0.
19
18
1
RO
Traffic Priority: Hardwired to 1 indicating that all streams will use VC1 if
it is enabled through the PCI Express registers.
00
RO
Stripe Control: This bit is only meaningful for input streams; therefore,
this bit is hardwired to 0.
17:16
15:5
0
RO
Reserved
Descriptor Error Interrupt Enable
0
R/W
4
3
0 = Disable
1 = An interrupt is generated when the Descriptor Error Status bit is set.
FIFO Error Interrupt Enable: This bit controls whether the occurrence of
a FIFO error (overrun for input or underrun for output) will cause an
interrupt or not. If this bit is not set, Bit 3 in the Status register will be set,
but the interrupt will not occur. Either way, the samples will be dropped.
0
R/W
Interrupt on Completion Enable: This bit controls whether or not an
interrupt occurs when a buffer completes with the IOC bit set in its
descriptor. If this bit is not set, Bit 2 in the Status register will be set, but
the interrupt will not occur.
0
R/W
2
Datasheet
161
INTEL [ INTEL ]
