Intel® HD Audio (D27:F0)
10.3.29 IRS—Immediate Command Status Register
Memory Address:
Default Value:
LBAR + 68h
0000h
Attribute:
Size:
R/W, R/WC, RO
16 bits
Default
Bit
and
Description
Access
0
RO
15:2
Reserved
Immediate Result Valid (IRV): This bit is set to 1 by hardware when a
new response is latched into the Immediate Response register (LBAR +
64). This is a status flag indicating that software may read the response
from the Immediate Response register.
0
1
R/WC
Software must clear this bit by writing a 1 to it before issuing a new
command so that the software may determine when a new response has
arrived.
Immediate Command Busy (ICB): When this bit is read as 0, it
indicates that a new command may be issued using the Immediate
Command mechanism. When this bit transitions from a 0 to a 1 (by
software writing a 1), the controller issues the command currently stored
in the Immediate Command register to the codec over the link. When the
corresponding response is latched into the Immediate Response register,
the controller hardware sets the IRV flag and clears the ICB bit back to 0.
0
R/W
0
NOTE: An Immediate Command must not be issued while the CORB/RIRB
mechanism is operating, otherwise the responses conflict. This
must be enforced by software.
10.3.30 DPBASE—DMA Position Base Address Register
Memory Address:
Default Value:
LBAR + 70h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
DMA Position Base Address: This field is the lower 32 bits of the DMA
Position Buffer Base Address. This register field must not be written when
any DMA engine is running or the DMA transfer may be corrupted. This
same address is used by the Flush Control and must be programmed with a
valid value before the Flush Control bit (LBAR+08h:Bit 1) is set.
0
R/W
31:7
00000b
RO
6:1
0
Reserved
DMA Position Buffer Enable: When this bit is set to 1, the controller will
write the DMA positions of each of the DMA engines to the buffer in the
main memory periodically (typically once per frame). Software can use this
value to know what data in memory is valid data.
0
R/W
160
Datasheet
INTEL [ INTEL ]
