Intel® HD Audio (D27:F0)
10.3.12 INTSTS—Interrupt Status Register
Memory Address:
Default Value:
LBAR + 24h
00000000h
Attribute:
Size:
RO
32 bits
Default
Bit
and
Description
Access
Global Interrupt Status (GIS): This bit is an OR of all the interrupt
status bits in this register.
0
RO
31
NOTE: This bit is not affected by the D3HOT to D0 transition.
Controller Interrupt Status (CIS): Status of general controller
interrupt.
1 = Indicates that an interrupt condition occurred due to a Response
Interrupt, a Response Buffer Overrun Interrupt, or a SDIN State
Change event. The exact cause can be determined by interrogating
other registers. This bit is an OR of all of the stated interrupt status
bits for this register.
0
RO
30
NOTES:
1.
This bit is set regardless of the state of the corresponding Interrupt
Enable bit, but a hardware interrupt will not be generated unless
the corresponding enable bit is set.
2.
This bit is not affected by the D3HOT to D0 transition.
0
RO
29:4
Reserved
0
RO
Output Stream 2 (OS2):
1 = Interrupt occurred on Output Stream 2.
3
2
1
0
0
RO
Output Stream 1 (OS1):
1 = Interrupt occurred on Output Stream 1.
0
RO
Input Stream 2 (IS2):
1 = Interrupt occurred on Input Stream 2.
0
RO
Input Stream 1 (IS1):
1 = Interrupt occurred on Input Stream 1.
152
Datasheet
INTEL [ INTEL ]
