Intel® HD Audio (D27:F0)
10.3.11 INTCTL—Interrupt Control Register
Memory Address:
Default Value:
LBAR + 20h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
Global Interrupt Enable (GIE): Global bit to enable device interrupt
generation.
1 = Intel® HD Audio function is enabled to generate an interrupt. This
control is in addition to any bits in the bus specific address space, such
as the Interrupt Enable bit in the PCI configuration space.
0
R/W
31
NOTE: This bit is not affected by the D3HOT to D0 transition.
Controller Interrupt Enable (CIE): Enables the general interrupt for
controller functions.
1 = Controller generates an interrupt when the corresponding status bit
gets set due to a Response Interrupt, a Response Buffer Overrun, and
State Change events.
0
R/W
30
NOTE: This bit is not affected by the D3HOT to D0 transition.
0
RO
29:4
Reserved
0
R/W
Output Stream 2 (OS2): This bit set and GE set enables INTSTS.OS2 to
generate an interrupt.
3
2
1
0
0
R/W
Output Stream 1 (OS1): This bit set and GE set enables INTSTS.OS1 to
generate an interrupt.
0
R/W
Input Stream 2 (IS2): This bit set and GE set enables INTSTS.IS2 to
generate an interrupt.
0
R/W
Input Stream 1 (IS1): This bit set and GE set enables INTSTS.IS1 to
generate an interrupt.
Datasheet
151
INTEL [ INTEL ]
