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319537-003US 参数 Datasheet PDF下载

319537-003US图片预览
型号: 319537-003US
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔系统控制器中心 [Intel System Controller Hub]
分类和应用: 控制器
文件页数/大小: 450 页 / 2593 K
品牌: INTEL [ INTEL ]
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Intel® HD Audio (D27:F0)  
10.3.8  
GSTS—Global Status Register  
Memory Address:  
Default Value:  
LBAR + 10h  
0000h  
Attribute:  
Size:  
R/WC, RO  
16 bits  
Default  
Bit  
and  
Description  
Access  
000h  
RO  
15:4  
Reserved  
Dock Mated Interrupt Status (DMIS): A 1 indicates that the dock  
mating or unmating process has completed. For the docking process it  
indicates that dock is electrically connected and that software may detect  
and enumerate the docked codecs. For the undocking process it indicates  
that the dock is electrically isolated and that software may report to the  
user that physical undocking may commence. This bit gets set to a 1 by  
hardware when the DM bit transitions from a 0 to a 1 (docking) or from a  
1 to a 0 (undocking). Note that this bit is set regardless of the state of the  
DMIE bit.  
0
3
R/WC  
Software clears this bit by writing a 1 to it. Writing a 0 to this bit has no  
effect.  
Dock Mated (DM): This bit effectively communicates to software that an  
Intel HD Audio docked codec is physically and electrically attached.  
Controller hardware sets this bit to 1 after the docking sequence triggered  
by writing a 1 to the Dock Attach (GCTL.DA) bit is completed  
(HDA_DOCKRST# deassertion). This bit indicates to software that the  
docked codec(s) may be discovered by the STATESTS register and then  
enumerated.  
0
RO  
2
Controller hardware sets this bit to 0 after the undocking sequence  
triggered by writing a 0 to the Dock Attach (GCTL.DA) bit is completed  
(DOCK_EN# deasserted). This bit indicates to software that the docked  
codec(s) may be physically undocked.  
This bit is Read Only. Writes to this bit have no effect.  
Flush Status: This bit is set to 1 by hardware to indicate that the flush  
cycle initiated when the Flush Control bit (LBAR + 08h, Bit 1) was set has  
completed. Software must write a 1 to clear this bit before the next time  
the Flush Control bit is set to clear the bit.  
0
1
0
R/WC  
0
RO  
Reserved  
Datasheet  
149