Integrated Graphics Device Registers (D2:F0,F1)
8.1.32
PMCAPID—Power Management Capabilities ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
D0–D1h
0001h
RWO, RO
16 bits
Size:
Bit
Access &
Default
Description
15:8
Next Capability Pointer (NEXT_PTR): This contains a pointer to next
item in capabilities list. This is the final capability in the list and must
be set to 00h.
RWO
00h
7:0
Capability Identifier (CAP_ID): SIG defines this ID is 01h for
power management.
RO
01h
8.1.33
PMCAP—Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
D2–D3h
0022h
RO
Size:
16 bits
This register is a Mirror of Function 0 with the same read/write attributes. The
hardware implements a single physical register common to both functions 0 and 1.
Bit
Access &
Default
Description
15:11
RO
00h
PME Support (PMES): This field indicates the power states in which
the IGD may assert PME#. Hardwired to 0 to indicate that the IGD
does not assert the PME# signal.
10
9
RO
0b
D2 Support (D2): The D2 power management state is not supported.
This bit is hardwired to 0.
RO
0b
D1 Support (D1): Hardwired to 0 to indicate that the D1 power
management state is not supported.
8:6
5
RO
000b
Reserved
RO
1b
Device Specific Initialization (DSI): Hardwired to 1 to indicate that
special initialization of the IGD is required before generic class device
driver is to use it.
4
3
RO
0b
Reserved
RO
0b
PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not
support PME# generation.
2:0
RO
010b
Version (VER): Hardwired to 010b to indicate that there are 4 bytes
of power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management Interface
Specification.
244
Datasheet
INTEL [ INTEL ]
