Integrated Graphics Device Registers (D2:F0,F1)
8.1.26
HSRW—Hardware Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
60–61h
0000h
RW
Size:
16 bits
Bit
Access &
Default
Description
15:0
RW
Reserved
0000h
8.1.27
MSI_CAPID— Message Signaled Interrupts Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
90–91h
D005h
RO;
Size:
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address. The
reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0]
@ 7Fh). In that case walking this linked list will skip this capability and instead go
directly to the PCI PM capability.
Bit
Access &
Default
Description
15:8
RO
D0h
Pointer to Next Capability (POINTNEXT): This contains a pointer
to the next item in the capabilities list which is the Power Management
capability.
7:0
RO
Capability ID (CAPID): Value of 05h identifies this linked list item
05h
(capability structure) as being for MSI registers.
240
Datasheet
INTEL [ INTEL ]
