Integrated Graphics Device Registers (D2:F0,F1)
8.2
IGD Configuration Register Details (D2:F1)
The Integrated Graphics Device registers are located in Device 2 (D2), Function 0 (F0)
and Function 1 (F1). This section provides the descriptions for the D2:F1 registers.
Table 8-2 provides an address map of the D2:F1registers listed in ascending order by
address offset. Detailed bit descriptions follow the table.
Table 8-2. Integrated Graphics Device Register Address Map (D2:F1)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
00–01h
02–03h
04–05h
06–07h
08h
VID2
DID2
Vendor Identification
8086h
29C3h
0000h
0090h
00h
RO
RO
Device Identification
PCI Command
PCICMD2
PCISTS2
RID2
RO, RW
RO
PCI Status
Revision Identification
Class Code Register
Cache Line Size
RO
09–0Bh
0Ch
CC
038000h
00h
RO
CLS
RO
0Dh
MLT2
Master Latency Timer
Header Type
00h
RO
0Eh
HDR2
80h
RO
10–13h
2C–2Dh
2E–2Fh
30–33h
34h
MMADR
SVID2
SID2
Memory Mapped Range Address
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
Capabilities Pointer
00000000h
0000h
0000h
00000000h
D0h
RW, RO
RO
RO
ROMADR
CAPPOINT
MINGNT
MAXLAT
MCAPPTR
CAPID0
RO
RO
3Eh
Minimum Grant
00h
RO
3Fh
Maximum Latency
00h
RO
44h
Mirror of Dev 0 Capabilities Pointer
Capability Identifier
E0h
RO
48–51h
00000000000
001090009h
RO
52–53h
MGGC
Mirror of Dev 0 GMCH Graphics
Control Register
0030h
RO
54–57h
58–5Bh
DEVEN
SSRW
Device Enable
000003DBh
00000000h
RO
RO
Mirror of Fun 0 Software Scratch
Read Write
5C–5Fh
60–61h
BSM
Mirror of Func0 Base of Stolen
Memory
07800000h
0000h
RO
RO
HSRW
Mirror of Dev2 Func0 Hardware
Scratch Read Write
Datasheet
247
INTEL [ INTEL ]
