Integrated Graphics Device Registers (D2:F0,F1)
8.1.28
MC—Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
92–93h
0000h
RO, RW
16 bits
Size:
System software can modify bits in this register, but the device is prohibited from
doing so. If the device writes the same message multiple times, only one of those
messages is ensured to be serviced. If all of them must be serviced, the device must
not generate the same message again until the driver services the earlier one.
Bit
15:8
7
Access &
Default
Description
Reserved
RO
00h
64 Bit Capable (64BCAP): Hardwired to 0 to indicate that the
function does not implement the upper 32 bits of the Message address
register and is incapable of generating a 64-bit memory address.
RO
0b
This may need to change in future implementations when addressable
system memory exceeds the 32b / 4 GB limit.
6:4
Multiple Message Enable (MME): System software programs this
field to indicate the actual number of messages allocated to this
device. This number will be equal to or less than the number actually
requested.
RW
000b
The encoding is the same as for the MMC field (Bits 3:1).
3:1
0
Multiple Message Capable (MMC): System Software reads this field
to determine the number of messages being requested by this device.
RO
000b
000 = 1
All other encodings are reserved.
RW
0b
MSI Enable (MSIEN): This bit controls the ability of this device to
generate MSIs.
Datasheet
241
INTEL [ INTEL ]
