Integrated Graphics Device Registers (D2:F0,F1)
8.1.29
MA—Message Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
94–97h
00000000h
RW, RO
Size:
32 bits
Bit
Access &
Default
Description
31:2
Message Address (MESSADD): Used by system software to assign
an MSI address to the device.
RW
00000000
h
The device handles an MSI by writing the padded contents of the MD
register to this address.
1:0
Force DWord Align (FDWORD): Hardwired to 0 so that addresses
assigned by system software are always aligned on a DWord address
boundary.
RO
00b
8.1.30
MD—Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
98–99h
0000h
RW
Size:
16 bits
Bit
Access &
Default
Description
15:0
Message Data (MESSDATA): Base message data pattern assigned
by system software and used to handle an MSI from the device.
RW
0000h
When the device must generate an interrupt request, it writes a 32-bit
value to the memory address specified in the MA register. The upper
16 bits are always set to 0. The lower 16 bits are supplied by this
register.
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Datasheet