欢迎访问ic37.com |
会员登录 免费注册
发布采购

317607-001 参数 Datasheet PDF下载

317607-001图片预览
型号: 317607-001
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 351 页 / 2481 K
品牌: INTEL [ INTEL ]
 浏览型号317607-001的Datasheet PDF文件第239页浏览型号317607-001的Datasheet PDF文件第240页浏览型号317607-001的Datasheet PDF文件第241页浏览型号317607-001的Datasheet PDF文件第242页浏览型号317607-001的Datasheet PDF文件第244页浏览型号317607-001的Datasheet PDF文件第245页浏览型号317607-001的Datasheet PDF文件第246页浏览型号317607-001的Datasheet PDF文件第247页  
Integrated Graphics Device Registers (D2:F0,F1)  
8.1.31  
GDRST—Graphics Debug Reset  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/2/0/PCI  
C0h  
00h  
RO, RW  
8 bits  
Size:  
Bit  
Access &  
Default  
Description  
7:2  
1
RO  
0h  
Reserved  
RO  
0b  
Graphics Reset Status (GRS):  
0 = Graphics subsystem not in Reset.  
1 = Graphics Subsystem in Reset as a result of Graphics Reset.  
This bit gets is set to a 1 when Graphics debug reset bit is set to a 1  
and the Graphics hardware has completed the debug reset sequence  
and all Graphics assets are in reset. This bit is cleared when Graphics  
Reset bit is set to a 0.  
0
RW  
0b  
Graphics Reset Enable (GR):  
1 = Assert display and render domain reset  
0 = De-assert display and render domain reset  
Render and Display clock domain resets should be asserted for at least  
20 us. Once this bit is set to a 1, all graphics core MMIO registers are  
returned to power on default state. All Ring buffer pointers are reset,  
command stream fetches are dropped and ongoing render pipeline  
processing is halted, state machines and State Variables returned to  
power on default state, Display and overlay engines are halted  
(garbage on screen). VGA memory is not available, Store DWORDs  
and interrupts are not ensured to be completed. Device 2 I/O registers  
are not available.  
Device 2 Configuration registers continue to be available while  
Graphics debug reset is asserted.  
Datasheet  
243