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317607-001 参数 Datasheet PDF下载

317607-001图片预览
型号: 317607-001
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 351 页 / 2481 K
品牌: INTEL [ INTEL ]
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Integrated Graphics Device Registers (D2:F0,F1)  
Bit  
2
Access &  
Default  
Description  
RO  
0b  
Reserved  
1
RO  
1b  
PCI Express Port (D1EN):  
0 = Bus 0, Device 1, Function 0 is disabled and hidden.  
1 = Bus 0, Device 1, Function 0 is enabled and visible.  
0
RO  
1b  
Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be  
disabled and is therefore hardwired to 1.  
8.1.24  
SSRW—Software Scratch Read Write  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/2/0/PCI  
58–5Bh  
00000000h  
RW  
Size:  
32 bits  
Bit  
Access &  
Default  
Description  
31:0  
RW  
Reserved  
00000000h  
8.1.25  
BSM—Base of Stolen Memory  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/2/0/PCI  
5C–5Fh  
07800000h  
RO  
Size:  
32 bits  
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD.  
From the top of low used DRAM, GMCH claims 1 to 64 MBs of DRAM for internal  
graphics if enabled.  
The base of stolen memory will always be below 4 GB. This is required to prevent  
aliasing between stolen range and the reclaim region.  
Bit  
Access &  
Default  
Description  
31:20  
Base of Stolen Memory (BSM): This register contains bits 31:20 of  
the base address of stolen DRAM memory. The host interface  
determines the base of Graphics Stolen memory by subtracting the  
graphics stolen memory size from TOLUD. See Device 0 TOLUD for  
more explanation.  
RO  
078h  
19:0  
Reserved  
RO  
00000h  
Datasheet  
239