Integrated Graphics Device Registers (D2:F0,F1)
8.1.20
MCAPPTR—Mirror of Dev 0 Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
44h
E0h
RO
8 bits
Size:
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
Bit
Access &
Default
Description
7:0
RO
E0h
Mirror of CAPPTR (MCAPPTR): Pointer to the offset of the first
capability ID register block. In this case the first capability is the
product-specific Capability Identifier (CAPID0).
8.1.21
CAPID0—Mirror of Dev0 Capability Identifier
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
48–51h
00000000000001090009h
RO
Size:
80 bits
Bit
Access &
Default
Description
79:26
RO
Reserved
00000000
00000h
27:24
23:16
15:8
7:0
RO
1h
CAPID Version (CAPIDV): This field has the value 0001b to identify
the first revision of the CAPID register definition.
RO
09h
CAPID Length (CAPIDL): This field has the value 09h to indicate the
structure length (9 bytes).
RO
00h
Next Capability Pointer (NCP): This field is hardwired to 00h
indicating the end of the capabilities linked list.
RO
09h
Capability Identifier (CAP_ID): This field has the value 1001b to
identify the CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
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Datasheet
INTEL [ INTEL ]
