Direct Memory Interface (DMI) Registers
7.1.12
DMILCTL—DMI Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/DMIBAR
88–89h
0000h
RW, RO
16 bits
Size:
This register allows control of DMI.
Bit
15:8
7
Access &
Default
Description
Reserved
RO
00h
Extended Synch (EXTSYNC):
RW
0b
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting
the L0s state and when in the Recovery state.
6:3
2
Reserved
RO
0h
Far-End Digital Loopback (FEDLB):
RW
0b
1:0
Active State Power Management Support (ASPMS): This field
controls the level of active state power management supported on the
given link.
RW
00b
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
222
Datasheet
INTEL [ INTEL ]
