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317607-001 参数 Datasheet PDF下载

317607-001图片预览
型号: 317607-001
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 351 页 / 2481 K
品牌: INTEL [ INTEL ]
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Direct Memory Interface (DMI) Registers  
7.1.7  
DMIVC0RSTS—DMI VC0 Resource Status  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/0/0/DMIBAR  
1A–1Bh  
0002h  
RO  
16 bits  
Size:  
This register reports the Virtual Channel specific status.  
Bit  
15:2  
1
Access &  
Default  
Description  
RO  
0000h  
Reserved.  
Virtual Channel 0 Negotiation Pending (VC0NP): This bit  
indicates the status of the process of Flow Control initialization. It is  
set by default on Reset, as well as whenever the corresponding Virtual  
Channel is Disabled or the Link is in the DL_Down state.  
RO  
1b  
It is cleared when the link successfully exits the FC_INIT2 state.  
0 = The VC negotiation is complete.  
1 = The VC resource is still in the process of negotiation (initialization  
or disabling).  
BIOS Requirement: Before using a Virtual Channel, software must  
check whether the VC Negotiation Pending fields for that Virtual  
Channel are cleared in both Components on a Link.  
0
RO  
0b  
Reserved  
7.1.8  
DMIVC1RCAP—DMI VC1 Resource Capability  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/0/0/DMIBAR  
1C–1Fh  
00008001h  
RO  
Size:  
32 bits  
Bit  
Access &  
Default  
Description  
31:16  
15  
RO  
00000h  
Reserved  
RO  
1b  
Reject Snoop Transactions (REJSNPT):  
0 = Transactions with or without the No Snoop bit set within the TLP  
header are allowed on this VC.  
1 = Any transaction without the No Snoop bit set within the TLP  
header will be rejected as an Unsupported Request.  
14:8  
7:0  
RO  
00h  
Reserved  
RO  
01h  
Port Arbitration Capability (PAC): Having only bit 0 set indicates  
that the only supported arbitration scheme for this VC is non-  
configurable hardware-fixed.  
Datasheet  
219