Direct Memory Interface (DMI) Registers
7.1.6
DMIVC0RCTL0—DMI VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/DMIBAR
14–17h
800000FFh
RO, RW
32 bits
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
RO
1b
Virtual Channel 0 Enable (VC0E): For VC0, this is hardwired to 1
and read only as VC0 can never be disabled.
30:27
26:24
23:20
19:17
RO
0h
Reserved
RO
000b
Virtual Channel 0 ID (VC0ID): Assigns a VC ID to the VC resource.
For VC0, this is hardwired to 0 and read only.
RO
0h
Reserved
RW
000b
Port Arbitration Select (PAS): This field configures the VC resource
to provide a particular Port Arbitration service. Valid value for this field
is a number corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource. Because only bit 0 of
that field is asserted.
This field will always be programmed to '1'.
Reserved
16:8
7:1
RO
000h
RW
7Fh
Traffic Class / Virtual Channel 0 Map (TCVC0M): This field
indicates the TCs (Traffic Classes) that are mapped to the VC resource.
Bit locations within this field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In order to remove one
or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels are
targeted at the given Link.
0
RO
1b
Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M): Traffic Class
0 is always routed to VC0.
218
Datasheet
INTEL [ INTEL ]
