Integrated Graphics Device Registers (D2:F0,F1)
8.1.2
DID—Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
02–03h
2982h
RO
Size:
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Bit
Access &
Default
Description
15:0
RO
Device Identification Number (DID): This is a 16 bit value
2982h
assigned to the GMCH Graphic device.
8.1.3
PCICMD2—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
04–05h
0000h
RO, RW
16 bits
Size:
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
Bit
15:11
10
Access &
Default
Description
RO
00h
Reserved
RW
0b
Interrupt Disable (INTDIS): This bit disables the device from
asserting INTx#.
0 = Enable the assertion of this device's INTx# signal.
1 = Disable the assertion of this device's INTx# signal. DO_INTx
messages will not be sent to DMI.
9
8
7
6
RO
0b
Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
RO
0b
SERR Enable (SERRE): Not Implemented. Hardwired to 0.
RO
0b
Address/Data Stepping Enable (ADSTEP): Not Implemented.
Hardwired to 0.
RO
0b
Parity Error Enable (PERRE): Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the IGD ignores
any parity error that it detects and continues with normal operation.
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Datasheet
INTEL [ INTEL ]
