Integrated Graphics Device Registers (D2:F0,F1)
8 Integrated Graphics Device
Registers (D2:F0,F1)
The Integrated Graphics Device (IGD) registers are located in Device 2 (D0), Function
0 (F0) and Function 1 (F1). This chapter provides the descriptions for these registers.
Section 8.1 provides the register descriptions for Device 2, Function 0. Section 8.2
provides the register descriptions for Device 2, Function 1.
8.1
Integrated Graphics Register Details (D2:F0)
Device 2, Function 0 contains registers for the internal graphics functions. Table 8-1
lists the PCI configuration registers in order of ascending offset address.
Function 0 can be VGA compatible or not, this is selected through bit 1 of GGC register
(Device 0, offset 52h).
Note: The following sections describe Device 2 PCI configuration registers only.
Table 8-1. Integrated Graphics Device Register Address Map (D2:F0)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
00–01h
02–03h
04–05h
06–07h
08h
VID2
DID
Vendor Identification
8086h
29C2h
0000h
0090h
00h
RO
RO
Device Identification
PCI Command
PCICMD2
PCISTS2
RID2
RO, RW
RO
PCI Status
Revision Identification
Class Code
RO
09–0Bh
0Ch
CC
030000h
00h
RO
CLS
Cache Line Size
RO
0Dh
MLT2
Master Latency Timer
Header Type
00h
RO
0Eh
HDR2
GMADR
80h
RO
18–1Fh
Graphics Memory Range Address
000000000
000000Ah
RW/L,
RO, RW
20–23h
2C–2Dh
2E–2Fh
30–33h
IOBAR
SVID2
SID2
IO Base Address
00000001h
0000h
RO, RW
RWO
RWO
RO
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
0000h
ROMADR
00000000h
224
Datasheet
INTEL [ INTEL ]
