Integrated Graphics Device Registers (D2:F0,F1)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
34h
3Eh
CAPPOINT
MINGNT
MAXLAT
MCAPPTR
CAPID0
Capabilities Pointer
90h
00h
00h
E0h
RO
RO
RO
RO
RO
Minimum Grant
3Fh
Maximum Latency
44h
Mirror of Dev 0 Capabilities Pointer
Mirror of Dev0 Capability Identifier
48–51h
000000000
000010900
09h
52–53h
54–57h
58–5Bh
5C–5Fh
60–61h
90–11h
MGGC
DEVEN
SSRW
GMCH Graphics Control Register
Device Enable
0030h
000003DBh
00000000h
07800000h
0000h
RO
RO
RW
RO
RW
R)
Software Scratch Read Write
Base of Stolen Memory
BSM
HSRW
Hardware Scratch Read Write
MSI_CAPID
Message Signaled Interrupts
Capability ID
D005h
C0h
GDRST
PMCAPID
PMCAP
PMCS
Graphics Debug Reset
00h
0001h
RO, RW/L
RWO, RO
RO
D0–D1h
D2–D3h
D4–D5h
E0–E1h
E4–E7h
FC–FFh
Power Management Capabilities ID
Power Management Capabilities
Power Management Control/Status
Software SMI
0022h
0000h
RO, RW
RW
SWSMI
ASLE
0000h
System Display Event Register
ASL Storage
00000000h
00000000h
RW
ASLS
RW
8.1.1
VID2—Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
00–01h
8086h
RO
Size:
16 bits
This register combined with the Device Identification register uniquely identifies any
PCI device.
Bit
Access &
Default
Description
15:0
RO
Vendor Identification Number (VID): PCI standard identification
8086h
for Intel.
Datasheet
225
INTEL [ INTEL ]
