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317607-001 参数 Datasheet PDF下载

317607-001图片预览
型号: 317607-001
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 351 页 / 2481 K
品牌: INTEL [ INTEL ]
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Direct Memory Interface (DMI) Registers  
7.1.10  
DMIVC1RSTS—DMI VC1 Resource Status  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/0/0/DMIBAR  
26–27h  
0002h  
RO  
16 bits  
Size:  
This register reports the Virtual Channel specific status.  
Bit  
15:2  
1
Access &  
Default  
Description  
RO  
0000h  
Reserved  
RO  
1b  
Virtual Channel 1 Negotiation Pending (VC1NP):  
0 = The VC negotiation is complete.  
1 = The VC resource is still in the process of negotiation (initialization  
or disabling).  
0
RO  
0b  
Reserved  
7.1.11  
DMILCAP—DMI Link Capabilities  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/0/0/DMIBAR  
84–87h  
00012C41h  
RO, RWO  
32 bits  
Size:  
This register indicates DMI specific capabilities.  
Bit  
Access &  
Default  
Description  
31:18  
17:15  
RO  
0000h  
Reserved  
RWO  
010b  
L1 Exit Latency (L1SELAT): This field indicates the length of time  
this Port requires to complete the transition from L1 to L0.  
010b = 2 us to less than 4 us.  
14:12  
RWO  
010b  
L0s Exit Latency (L0SELAT): This field indicates the length of time  
this Port requires to complete the transition from L0s to L0.  
010 = 128 ns to less than 256 ns  
11:10  
9:4  
RO  
11b  
Active State Link PM Support (ASLPMS): L0s & L1 entry  
supported.  
RO  
Max Link Width (MLW): This field indicates the maximum number  
04h  
of lanes supported for this link.  
3:0  
RO  
1h  
Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.  
Datasheet  
221