欢迎访问ic37.com |
会员登录 免费注册
发布采购

317607-001 参数 Datasheet PDF下载

317607-001图片预览
型号: 317607-001
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 351 页 / 2481 K
品牌: INTEL [ INTEL ]
 浏览型号317607-001的Datasheet PDF文件第213页浏览型号317607-001的Datasheet PDF文件第214页浏览型号317607-001的Datasheet PDF文件第215页浏览型号317607-001的Datasheet PDF文件第216页浏览型号317607-001的Datasheet PDF文件第218页浏览型号317607-001的Datasheet PDF文件第219页浏览型号317607-001的Datasheet PDF文件第220页浏览型号317607-001的Datasheet PDF文件第221页  
Direct Memory Interface (DMI) Registers  
7.1.4  
DMIPVCCTL—DMI Port VC Control  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/0/0/DMIBAR  
0C–0Dh  
0000h  
RO, RW  
16 bits  
Size:  
Bit  
15:4  
3:1  
Access &  
Description  
Default  
RO  
000h  
Reserved  
RW  
000b  
VC Arbitration Select (VCAS): This field will be programmed by  
software to the only possible value as indicated in the VC Arbitration  
Capability field.  
See the PCI express specification for more details.  
Reserved  
0
RO  
0b  
7.1.5  
DMIVC0RCAP—DMI VC0 Resource Capability  
B/D/F/Type:  
Address Offset:  
Default Value:  
Access:  
0/0/0/DMIBAR  
10–13h  
00000001h  
RO  
Size:  
32 bits  
Bit  
31:16  
15  
Access &  
Description  
Default  
RO  
00000h  
Reserved  
RO  
0b  
Reject Snoop Transactions (REJSNPT):  
0 = Transactions with or without the No Snoop bit set within the TLP  
header are allowed on this VC.  
1 = Any transaction without the No Snoop bit set within the TLP  
header will be rejected as an Unsupported Request.  
14:8  
7:0  
RO  
00h  
Reserved  
RO  
01h  
Port Arbitration Capability (PAC): Having only bit 0 set indicates  
that the only supported arbitration scheme for this VC is non-  
configurable hardware-fixed.  
Datasheet  
217  
 
 复制成功!