PCI Express* Registers (D1:F0)
6.1.52
VC0RCTL—VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
114–117h
800000FFh
RO, RW
Size:
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
Description
31
VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only
as VC0 can never be disabled.
RO
1b
30:27
26:24
23:8
7:1
Reserved
RO
0h
VC0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0, this
is hardwired to 0 and read only.
RO
000b
Reserved
RO
0000h
TC/VC0 Map (TCVC0M): This field indicates the TCs (Traffic
Classes) that are mapped to the VC resource. Bit locations within this
field correspond to TC values. For example, when bit 7 is set in this
field, TC7 is mapped to this VC resource. When more than one bit in
this field is set, it indicates that multiple TCs are mapped to the VC
resource. To remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
RW
7Fh
0
TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0.
RO
1b
208
Datasheet
INTEL [ INTEL ]
