PCI Express* Registers (D1:F0)
6.1.56
LE1D—Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
150–153h
00000000h
RO, RWO
32 bits
Size:
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
00h
Target Port Number (TPN): This field specifies the port number
associated with the element targeted by this link entry (Express Port).
The target port number is with respect to the component that contains
this element as specified by the target component ID.
23:16
15:2
1
RWO
00h
Target Component ID (TCID): This field identifies the physical or
logical component that is targeted by this link entry.
RO
0000h
Reserved
RO
0b
Link Type (LTYP): This field indicates that the link points to
memory-mapped space (for RCRB). The link address specifies the 64-
bit base address of the target RCRB.
0
RWO
0b
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
6.1.57
LE1A—Link Entry 1 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
158–15Fh
0000000000000000h
RO, RWO
64 bits
Size:
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
63:32
RO
00000000
h
Reserved
31:12
11:0
RWO
00000h
Link Address (LA): This field contains the memory-mapped base
address of the RCRB that is the target element (Express Port) for this
link entry.
RO
Reserved
000h
Datasheet
211
INTEL [ INTEL ]
