PCI Express* Registers (D1:F0)
6.1.54
RCLDECH—Root Complex Link Declaration Enhanced
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
140–143h
00010005h
RO
Size:
32 bits
This capability declares links from this element (PEG) to other elements of the root
complex component to which it belongs. See PCI Express specification for
link/topology declaration requirements.
Bit
Access &
Default
Description
31:20
19:16
RO
000h
Pointer to Next Capability (PNC): This is the last capability in the
PCI Express extended capabilities list
RO
1h
Link Declaration Capability Version (LDCV): Hardwired to 1 to
indicate compliances with the 1.1 version of the PCI Express
specification.
15:0
RO
0005h
Extended Capability ID (ECID): Value of 0005h identifies this linked
list item (capability structure) as being for PCI Express Link
Declaration Capability.
6.1.55
ESD—Element Self Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
144–147h
02000100h
RO, RWO
32 bits
Size:
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
Access &
Default
Description
31:24
RO
02h
Port Number (PN): This field specifies the port number associated
with this element with respect to the component that contains this
element. This port number value is utilized by the Express port of the
component to provide arbitration to this Root Complex Element.
23:16
15:8
RWO
00h
Component ID (CID): This field identifies the physical component
that contains this Root Complex Element.
RO
01h
Number of Link Entries (NLE): This field indicates the number of
link entries following the Element Self Description. This field reports 1
(to Express port only as we don't report any peer-to-peer capabilities
in our topology).
7:4
3:0
RO
0h
Reserved
RO
0h
Element Type (ET): This field indicates the type of the Root Complex
Element. Value of 0h represents a root port.
210
Datasheet
INTEL [ INTEL ]
