PCI Express* Registers (D1:F0)
6.1.49
PVCCAP2—Port VC Capability Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
108–10Bh
00000000h
RO
Size:
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Bit
Access &
Default
Description
31:24
VC Arbitration Table Offset (VCATO): This field indicates the
location of the VC Arbitration Table. This field contains the zero-based
offset of the table in DQWORDS (16 bytes) from the base address of
the Virtual Channel Capability Structure. A value of 0 indicates that
the table is not present (due to fixed VC priority).
RO
00h
23:0
Reserved
RO
0s
6.1.50
PVCCTL—Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
10C–10Dh
0000h
RO, RW
16 bits
Size:
Bit
15:4
3:1
Access &
Description
Default
RO
000h
Reserved
RW
000b
VC Arbitration Select (VCAS): This field will be programmed by
software to the only possible value as indicated in the VC Arbitration
Capability field. Since there is no other VC supported than the
default, this field is reserved.
0
RO
0b
Reserved
206
Datasheet
INTEL [ INTEL ]
