PCI Express* Registers (D1:F0)
6.1.47
VCECH—Virtual Channel Enhanced Capability Header
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
100–103h
14010002h
RO
Size:
32 bits
This register indicates PCI Express device Virtual Channel capabilities. Extended
capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability
structures.
Bit
Access &
Default
Description
31:20
Pointer to Next Capability (PNC): The Link Declaration Capability is
the next in the PCI Express extended capabilities list.
RO
140h
19:16
15:0
PCI Express Virtual Channel Capability Version (PCI
EXPRESS*VCCV): Hardwired to 1 to indicate compliances with the 1.1
version of the PCI Express specification.
RO
1h
Extended Capability ID (ECID): Value of 0002 h identifies this
linked list item (capability structure) as being for PCI Express Virtual
Channel registers.
RO
0002h
6.1.48
PVCCAP1—Port VC Capability Register 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/MMR
104–107h
00000000h
RO
Size:
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Bit
Access &
Default
Description
31:7
Reserved
RO
0000000h
6:4
Low Priority Extended VC Count (LPEVCC): This field indicates the
number of (extended) Virtual Channels in addition to the default VC
belonging to the low-priority VC (LPVC) group that has the lowest
priority with respect to other VC resources in a strict-priority VC
Arbitration.
RO
000b
The value of 0 in this field implies strict VC arbitration.
Reserved
3
RO
0b
2:0
Extended VC Count (EVCC): This field indicates the number of
(extended) Virtual Channels in addition to the default VC supported by
the device.
RO
000b
Datasheet
205
INTEL [ INTEL ]
