PCI Express* Registers (D1:F0)
6.1.46
PEGLC—PCI Express*-G Legacy Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
EC–EFh
00000000h
RW, RO
Size:
32 bits
This register controls functionality that is needed by Legacy (non-PCI Express aware)
operating systems during run time.
Bit
Access &
Default
Description
31:3
RO
00000000
h
Reserved
2
1
RW
0b
PME GPE Enable (PMEGPE):
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received
(Assert_PMEGPE and Deassert_PMEGPE messages on DMI). This
enables the GMCH to support PMEs on the PEG port under legacy
operating systems.
RW
0b
Hot-Plug GPE Enable (HPGPE):
0 = Do not generate GPE Hot-Plug message when Hot-Plug event is
received.
1 = Generate a GPE Hot-Plug message when Hot-Plug Event is
received (Assert_HPGPE and Deassert_HPGPE messages on DMI).
This enables the GMCH to support Hot-Plug on the PEG port under
legacy operating systems.
0
RW
0b
General Message GPE Enable (GENGPE):
0 = Do not forward received GPE assert/de-assert messages.
1 = Forward received GPE assert/de-assert messages. These general
GPE message can be received via the PEG port from an external
Intel device (i.e., PxH) and will be subsequently forwarded to the
ICH (via Assert_GPE and Deassert_GPE messages on DMI). For
example, PxH might send this message if a PCI Express device is
hot plugged into a PxH downstream port.
204
Datasheet
INTEL [ INTEL ]
