PCI Express* Registers (D1:F0)
Bit
Access &
Default
Description
Power Fault Detected (PFD): If a Power Controller that supports
power fault detection is implemented, this bit is set when the Power
Controller detects a power fault at this slot. Note that, depending on
hardware capability, it is possible that a power fault can be detected
at any time, independent of the Power Controller Control setting or
the occupancy of the slot. If power fault detection is not supported,
this bit must not be set.
1
RO
0b
Attention Button Pressed (ABP): If an Attention Button is
implemented, this bit is set when the attention button is pressed. If an
Attention Button is not supported, this bit must not be set.
0
RO
0b
6.1.44
RCTL—Root Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
BC–BDh
0000h
RO, RW
16 bits
Size:
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
Bit
15:4
3
Access &
Default
Description
RO
000h
Reserved
RW
0b
PME Interrupt Enable (PMEIE):
0 = No interrupts are generated as a result of receiving PME messages.
1 = Enables interrupt generation upon receipt of a PME message as
reflected in the PME Status bit of the Root Status Register. A PME
interrupt is also generated if the PME Status bit of the Root Status
Register is set when this bit is set from a cleared state.
2
RW
0b
System Error on Fatal Error Enable (SEFEE): This bit controls the
Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = SERR should be generated if a fatal error is reported by any of the
devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
202
Datasheet
INTEL [ INTEL ]
