PCI Express* Registers (D1:F0)
Bit
Access &
Default
Description
1
RW
0b
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE): This bit controls the Root Complex's response to non-
fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = SERR should be generated if a non-fatal error is reported by any of
the devices in the hierarchy associated with this Root Port, or by
the Root Port itself.
0
RW
0b
System Error on Correctable Error Enable (SECEE): This bit
controls the Root Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = SERR should be generated if a correctable error is reported by any
of the devices in the hierarchy associated with this Root Port, or
by the Root Port itself.
6.1.45
RSTS—Root Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
C0–C3h
00000000h
RO, RWC
32 bits
Size:
This register provides information about PCI Express Root Complex specific
parameters.
Bit
31:18
17
Access &
Default
Description
RO
0000h
Reserved
RO
0b
PME Pending (PMEP):
1 = Another PME is pending when the PME Status bit is set. When the
PME Status bit is cleared by software; the PME is delivered by
hardware by setting the PME Status bit again and updating the
Requestor ID appropriately. The PME pending bit is cleared by
hardware if no more PMEs are pending.
16
RWC
0b
PME Status (PMES):
1 = PME was asserted by the requestor ID indicated in the PME
Requestor ID field. Subsequent PMEs are kept pending until the
status register is cleared by writing a 1 to this field.
15:0
RO
PME Requestor ID (PMERID): This field indicates the PCI requestor
0000h
ID of the last PME requestor.
Datasheet
203
INTEL [ INTEL ]
