PCI Express* Registers (D1:F0)
6.1.3
PCICMD1—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
04–05h
0000h
RO, RW
16 bits
Size:
Bit
15:11
10
Access &
Description
Default
RO
00h
Reserved
RW
0b
INTA Assertion Disable (INTAAD): This bit 0nly affects interrupts
generated by the device (PCI INTA from a PME or Hot Plug event)
controlled by this command register. It does not affect upstream MSIs,
upstream PCI INTA–INTD assert and de-assert messages.
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any
INTA emulation interrupts already asserted must be de-asserted
when this bit is set.
9
8
RO
0b
Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented.
Hardwired to 0.
RW
0b
SERR# Message Enable (SERRE1): Controls Device 1 SERR#
messaging. The GMCH communicates the SERR# condition by sending
an SERR message to the ICH. This bit, when set, enables reporting of
non-fatal and fatal errors detected by the device to the Root Complex.
Note that errors are reported if enabled either through this bit or
through the PCI Express specific bits in the Device Control Register.
0 = The SERR message is generated by the GMCH for Device 1 only
under conditions enabled individually through the Device Control
Register.
1 = The GMCH is enabled to generate SERR messages which will be
sent to the ICH for specific Device 1 error conditions
generated/detected on the primary side of the virtual PCI to PCI
bridge (not those received by the secondary side). The status of
SERRs generated is reported in the PCISTS1 register.
7
6
RO
0b
Reserved: Not Applicable or Implemented. Hardwired to 0.
RW
0b
Parity Error Response Enable (PERRE): This bit controls whether
or not the Master Data Parity Error bit in the PCI Status register can
bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
5
4
RO
0b
VGA Palette Snoop (VGAPS): Not Applicable or Implemented.
Hardwired to 0.
RO
0b
Memory Write and Invalidate Enable (MWIE): Not Applicable or
Implemented. Hardwired to 0.
166
Datasheet
INTEL [ INTEL ]
