DRAM Controller Registers (D0:F0)
5.2.31
EPC0DRB2— ME Channel 0 DRAM Rank Boundary Address
2
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A04–A05h
0000h
RO, RW
16 bits
Size:
See C0DRB0 register.
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
RW
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2):
000h
5.2.32
EPC0DRB3— ME Channel 0 DRAM Rank Boundary Address
3
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/MCHBAR
A06–A07h
0000h
RW, RO
16 bits
Size:
See C0DRB0 register.
Bit
15:10
9:0
Access &
Default
Description
RO
000000b
Reserved
RW
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3):
000h
Datasheet
141
INTEL [ INTEL ]
